In the fabrication of integrated circuits, it is often necessary to form a large number of transistors on a single chip. These transistors are interconnected to form logic gates, flip-flops, memory cells, and a wide variety of other devices. A gate array is an array of transistor circuits which utilize the same base cell for many different applications. In this configuration, only the final interconnect levels of the multi-level device are specifically designed for any given application. The initial level, known as the base cell, is the same for each implementation. In typical applications, the base cell includes a heavily-doped moat region separated by a lightly-doped channel region and a gate that insulatively overlies the channel region.
One type of gate array includes some moat regions which have P-doped silicon and other moat regions that include N-doped silicon. These regions can be used to create P-channel and N-channel devices, respectively. One example of an application that uses both conductivity types of channels is a CMOS (complimentary metal oxide semi-conductor device). Many gate array applications electrically connect the gates of adjacent base cells to one another. This electrical connection is often made when the gates are formed during the base cell fabrication. Connected gates are common in CMOS devices such as inverters or NAND gates, for example. In other applications, such as single or complimentary transfer gates or for some dynamic circuits, for example, it is inefficient to "pre-connect" (i.e., connect during base cell fabrication) the gates of adjacent cells. To solve the problem of having both gates that are connected and gates that are not connected, the entire base cell may be redesigned for each application. This custom design approach, however, is costly because more levels of the multi-level fabrication must be built for each specific application. Another solution may be to either connect all base cell gate pairs or leave all base cell gate pairs disconnected. This solution, however, leads to inefficient base cell usage.
Another consideration for CMOS applications is that the substrate be biased to equal or less than the source potential to prevent forward biasing. The substrate potential is given through a highly-doped diffusion. To make an ohmic or resistive contact, N.sup.+ and P.sup.+ diffusions are chosen for N.sup.- and P.sup.- substrates, respectively. In these configurations, essentially no current flows to the substrate from ground and the power supply. Therefore, a wide range of resistance values are acceptable for the substrate contact. In gate arrays, all diffusions into the moat area are pre-determined, regardless of the position of the contacts and metal lines. In order to employ a conventional substrate contact in gate arrays, therefore, N.sup.+ contacts for the P-channel resistor and P.sup.+ contacts for the N-channel resistor should be pre-placed throughout the gate array regardless of their necessity. This design, however, wastes a significant amount of silicon area and, thereby, degrades the overall efficiency of the gate array implementation.